| |
| ABT |
Advanced BiCMOS Technology |
| ACPI |
Advanced Configuration and Power Interface (power management specification) |
| AGV |
Automated Guided Vehicle (robotic material transferring vehicle) |
| ALF |
Advanced Library Format (IEEE-1603/
IEC-62265 standard used in
ASIC design)
|
| ALSTTL |
Advanced Low-power Schottky TTL) |
| AMBA |
Advance Microcontroller Bus Architecture (Open standard for on-chip bus specification) |
| AMP |
Asymmetric Multi-Processing (symmetric - SMP) |
| AND |
AND logic gate
(other logic -
NAND,
NOR,
XNOR,
OR,
XOR,
NOT
) |
| ASCI |
Accelerated Strategic Computing Initiative |
| ASIC |
Application-Specific Integrated Circuit |
| ATMP |
Assembly, Test, Mark, and Packaging (electronic chips etc.) |
| AWG |
Arbitrary Waveform Generator |
| AZ/EL/POL |
Azimuth, Elevation, Polar axes/co-ordinates in an antenna design/mounting |
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| BEOL |
Back End of Line
(IC fabrication;
front - FEOL) |
| BSAC |
Bit Sliced Arithmetic Coding
(audio coding algorithm developed by Samsung) |
| BSDL |
Boundary Scan Description Language (hardware description language) |
| BTL |
Backplane Transceiver Logic
(other logic GTL)
|
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| CAD |
Computer Aided Design |
| CAE |
Computer Aided Engineering |
| CAMAC |
Computer-Aided Measurement And Control (data acquisition standard) |
| CASE |
Computer Aided Software Engineering |
| CAWE |
Computer Aided Web Engineering |
| CBSE |
Component Based Software Engineering |
| CFAR |
Constant False Alarm Rate (Radar) |
| CIR |
Complex Impluse Response |
| CMRR |
Common Mode Rejection Ratio (CMRR = Differential mode gain/Common-mode gain) |
| |
CMRR = 20*log(Ad/|Acm|) dB |
| CENELEC |
Comité Européen de Normalisation Électrotechnique |
| CLCC |
Ceramic Leaded Chip Carrier |
| CML |
Current Mode Logic
(Logic Gate design) |
| CMOS |
Complementary Metal Oxide
Semiconductor |
| CMVR |
Common mode voltage range (operational amplifier) |
| COGO |
Co-ordinate Geometry (software for land surveying, mapping etc.) |
| CSO |
Composite Second Order
(microwave distortion) |
| CSP |
Chip Scale Package |
| CSP |
Chip Size Package |
| CTS |
Clock Transition System |
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| DCS |
Distributed Control System |
| DEF |
Design Exchange Format (circuit design,
VLSI) |
| DEM |
Distributed-Element Model
(TLM; electrical power transmission) |
| DFL |
Distributed Feedback Laser |
| DFM |
Design For Manufacturability |
| DFT |
Design For Test/Testability |
| DIB |
Dual Independent Bus architecture |
| DLC |
Dynamic Load Control (electric grid, battery charging, etc.) |
| DMA |
Direct Memory Access |
| DRBG |
Deterministic Random bit Generator (PRNG) |
| DTL |
Diode-Transistor Logic |
| DUT |
Device Under Test |
| DXF |
Drawing Exchange Format (AutoCAD drawing file format) |
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| EBR |
Electron Beam Recording |
| ECAD |
Electrical/Electronic engineering CAD |
| ECL |
Emitter-Coupled Logic |
| ECO |
Engineering Change Order |
| EDA |
Electronic Design Automation |
| EEL |
Electric Echo Loss |
| EIA |
Electronic Industry Alliance |
| EMR |
Electromagnetic Radiation |
| EMRP |
Effective Monopole Radiated Power (Europe) |
| ENOB |
Effective Number of Bits |
| EPT |
Extended Page Tables (used to reduce transitions for
VMM
to manage
memory
virtualization)
|
| ESD |
Electrostatic Discharge |
| ESR |
Equivalent Series Resistance |
| ESL |
Equivalent Series Inductance (L - Inductance) |
| ESPRIT |
Estimating Signal Parameter via Rotational Invariance Techniques |
| ETO |
Engineering-to-Order (customized product) |
| ETS |
Equivalent Time Sampling |
| EUT |
Equipment Under Test |
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| FEA |
Field Emitter Array |
| FEA |
Finite Element Analysis |
| FELV |
Functional Extra-Low Voltage |
| FEOL |
Front End of Line
(IC fabrication;
back - BEOL) |
| FMCW |
Frequency Modulated Continuous Wave
(radar devices) |
| FPSLIC |
Field Programmable System Level Integrated Circuit |
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| GART |
Graphic Address Remapping Table |
| GPR |
Ground Penetrating Radar |
| GTL |
Gunning Transceiver Logic (invented by William Gunning;
other logic BTL) |
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| HTRB |
High Temperature Reverse Bias |
| HVPE |
Hydride Vapour Phase Epitaxy
(semiconductors manufacture) |
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| ICEM |
Integrated Computer aided Engineering and Manufacturing |
| ICSP |
In-Circuit Serial Programming |
| IDL |
Integral Non-Linearity (a measure of performance in
ADC and
DAC converters) |
| IEC |
International Engineering Consortium |
| IEEE |
Institute of Electrical and Electronic Engineers |
| IGES |
Initial Graphics Exchange Specification |
| |
IGES: vendor-neutral file format used in CAD Systems |
| IMD |
Intermodulation Distortion |
| IOMMU |
Input Output
Memory
Management Unit |
| IRF |
Impulse Response Function (signal processing) |
| ISP |
In-System Programming |
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| JEDEC |
Joint Electron Device Engineering Council |
| JEIDA |
Refer
JEIDA
|
| JESSI |
Joint European Submicron Silicon Initiative |
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| LCCC |
Leadless Ceramic Chip Carrier |
| LCLV |
Liquid-Crystal Light-Valve |
| LDA |
Laser
Doppler Anemometer
|
| LDMOS |
Laterally Diffused MOS |
| LDV |
Laser
Doppler Velocimeter
|
| LET |
Linear Energy Transfer |
| LFSR |
Linear Feedback Shift Register (used in creating
PRN) |
| LIGBT |
Lateral Insulated
Gate Bipolar
Transistor |
| LLP |
Lead-less Lead-frame Package |
| LPN |
Logical Page Number (
MMU
) |
| LQR |
Linear Quadratic Regulator
|
| LSTTL |
Low power Schottky TTL |
| LVCMOS |
Low Voltage CMOS |
| LVDS |
Low Voltage Differential Signalling (EIA-644) |
| LVTTL |
Low Voltage TTL |
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| MBE |
Model-Based Engineering |
| MBSE |
Model-Based Systems Engineering |
| MCAD |
Mechanical engineering CAD |
| MCBF |
Mean Cycles Between Failures |
| MCW |
Multi-Carrier Waveform |
| MDOF |
Multi Degree of Freedom
(single - SDOF) |
| MLCC |
Metal Leaded Chip Carrier |
| MOS |
Metal Oxide
Semiconductor |
| MPN |
Machine Page Number (
MMU
) |
| MTBF |
Mean Time Between Failures |
| MTBO |
Mean Time Between Outages |
| MVDR |
Minimum Variance Distortionless Response (used in antenna, radar, microphone design) |
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| NDR |
Negative Differential Resistence (transistor) |
| NEC |
Numerical Electromagnetics Code (antenna modelling
Fortran program, initial version created at
LLNL) |
| NEP |
Noise Equivalent Power; measure of photodetector sensitivity [NEP = P/SNR] |
| |
NEP: Signal power that results in SNR of 1 in 1 Hz output bandwidth |
| NLDM |
Nonlinear Delay Model |
| NMRR |
Normal-Mode Rejection Ratio
NMRR = 20 * log(Vin/Verror) |
| |
Vin is input and Verror
is error voltage respectively in
DMM
|
| NRE |
Non Recurring Engineering (refers to one time research, engineering/design of a product and costs) |
| NSE |
Noise Spectrum Equalizer |
| NTC |
Negative Temperature Coefficient of resistance |
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| OCM |
On-Chip Memory |
| OFDM |
Orthogonal FDM |
| OSR |
Over-Sampling Ratio
(ADC) |
| |
OSR = (sampling or clock frequency)/(2 x Analog signal
bandwidth) |
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| PAE |
Physical Address Extension (
Memory
)
|
| PAPR |
Peak to Average Power Ratio |
| PAR |
Peak to Average Ratio |
| PARD |
Periodic and Random Deviation |
| PDL |
Program Description Language |
| PDS |
Processor Direct Slot |
| PEEL |
Programmable Electrically Erasable Logic |
| PELV |
Protected Extra-Low Voltage |
| PID |
Proportional-Integral-Derivative (controller in robots) |
| PIND |
Particle Impact Noise Detection |
| PIPO |
Parallel-In to Parallel-Out (shift register) |
| PISO |
Parallel-In to Serial-Out (shift register) |
| PIV |
Peak Inverse Voltage (diode) |
| PLC |
Planar Lightwave Circuits (used in
PON) |
| PLCC |
Plastic Leaded Chip Carrier |
| PLL |
Phase Locked Loop |
| PPN |
Physical Page Number (
MMU
) |
| PRBS |
Pseudo Random Binary Sequence |
| PRBS |
Pseudo Random Bit Sequence |
| PRF |
Pulse Repetition Frequency |
| PRI |
Pulse Repetition Interval |
| PRN |
Pseudo Random Number |
| PRNG |
Pseudo Random Number Generator |
| PRR |
Pulse Repetition Rate |
| PRV |
Peak Reverse Voltage (diode);
same as PIV |
| PSD |
Power Spectral Density |
| PSNR |
Peak Signal to Noise Ratio |
| PSRR |
Power Supply Rejection Ratio (PSRR =
10log10(ΔVsupply2Av2/ΔVout2) dB
|
| |
Av is voltage gain |
| PTC |
Positive Temperature Coefficient of resistance |
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| QFE |
Quick Fix Engineering (refers to application/software hotfix, patches, hardware etc.) |
| QSOP |
Quarter Small Outline Package
(SOIC)
|
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| ROV |
Remotely Operated Vehicle (typically underwater robotic vehicle) |
| RTL |
Resistor-Transistor Logic |
| RTP |
Rapid Thermal Processing
(semiconductor manufacturing) |
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| SAW |
Surface Acoustic Wave |
| SBDIP |
Side Braze Dual-In-line Package |
| SCADA |
Supervisory Control and Data Acquisition (software) |
| SCARA |
Selective Compliance Assembly Robot Arm (industrial robot) |
| SCL |
Source Coupled Logic
(Logic Gate design) |
| SCPI |
Standard Commands for Programmable Instruments |
| SDBGA |
Stacked Die Ball Grid Array |
| |
SDBGA: Super Dissipation Ball Grid Array |
| SDOF |
Single Degree of Freedom
(multi - MDOF)
|
| SECAM |
Systems Engineering Capability Assessment Model |
| SEE |
Single Event Effects (ASIC/FPGA) |
| SEL |
Single Event Latchup
(laser testing) |
| SEL |
Surface Emitting Laser
(VCSEL) |
| SELV |
Separated or Safety Extra-Low Voltage |
| SET |
Single Event Transient
(ASIC/FPGA) |
| SEU |
Single Event Upset (ASIC/FPGA) |
| SFDR |
Spurious Free Dynamic Range |
| SICL |
Standard Instrument Control Library |
| SINAD |
Signal to Noise and Distortion Ratio |
| SIO |
Serial Input/Output (I/O) |
| SIPO |
Serial-In to Parallel-Out (shift register) |
| SIR |
Surface Insulation Resistance |
| SISO |
Serial-In to Serial-Out (shift register) |
| SLC |
Surface Laminar Circuit |
| SLICC |
Slightly Larger than
IC Carrier |
| SMA |
Surface Mount Assembly |
| SMOBC |
Solder Mask Over Bare Copper |
| SMRT |
Surface Mount and Reflow Technology |
| SMT |
Surface Mount Technology |
| SNR |
Signal to Noise (S/N) ratio (SNR formulation) |
| SOIC |
Small Outline Integrated Circuit |
| SPDM |
Scalable Polynomial Delay Model |
| Spice |
Simulation Program with Integrated Circuit Emphasis |
| SRC |
Scalable Sampling Rate |
| SSI |
Signal Strength Indicator |
| SSOP |
Shrink Small Outline Package
(SOIC)
|
| SST |
Simultaneous Self Test |
| SST |
Solid State Technology |
| STTL |
Schottky TTL |
| STW |
Surface Transversal Wave |
| SH-SAW |
Shear Horizontal SAW |
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| TAV |
Transverse Acoustoelectric Voltage |
| TCC |
Temperature Coefficient of Capacitance |
| TCR |
Temperature Coefficient of Resistance;
TCR=(R - R0)/(R0 x (T - T0)) |
| TEM |
Transverse Electro-Magnetic (mode of propogation restricted to transverse) |
| THB |
Temperature, Humidity Bias |
| THD |
Total Harmonic Distortion |
| TLM |
Transmission-Line Model
(DEM) |
| TSOP |
Thin Small Outline Package
(SOIC)
|
| TSPCR |
True Single-Phase Clocked Register |
| TSSOP |
Thin Shrink Small Outline Package
|
| TSTN |
Triple Super Twisted Nematic |
| TTL |
Transistor-Transistor Logic |
| TTS |
Timed Transition Systems |
| TVI |
Television Interfence (signal) |
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| USAT |
Ultra Small Aperture Terminal
|
| UVLO |
Under Voltage Lockout
|
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| Vac |
Voltage alternating current |
| Vcc |
Designation of (collector) supply voltage in an
IC |
| VCSEL |
Vertical Cavity SEL |
| Vdc |
Voltage direct current |
| Vdd |
Designation of drain voltage (pin) in an
IC |
| Vee |
Designation of Emitter voltage (pin) in an
IC |
| VISA |
Virtual Instrument Software Architecture |
| VMM |
Virtual Machine Monitor |
| VSAT |
Very Small Aperture Terminal (satellite communication system used in
GPS,
GSM etc.)
|
| VSOP |
Very Small Outline Package
(SOIC)
|
| Vss |
Designation of Source voltage (pin) in an
IC |
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| WLP |
Wafer Level Package |
| WSI |
Wafer-Scale Integration |
| WUT |
Wafer Under Test |
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| ZCS |
Zero Current Switching |
| ZIL |
Zigzag In-Line (pin arrangement in chips) |
| ZIP |
Zigzag Inline Package (chip package) |
| ZVS |
Zero Voltage Switching |
| ZWS |
Zero Wait State (computer chipsets designed to process memory instantaneously with least/no waiting) |
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